With advances in the electronic industry, demand for higher-performance, faster-speed, and smaller-sized (compact) electronic components are increasing. Along with this trend, one of the present semiconductor package technologies is to stack (e.g., mount) a plurality of memory chips on a single package substrate. If the memory chips are stacked, however, an input capacitance of a resultant semiconductor package including the stacked memory chips increases, thereby resulting in a decrease in speed. Further, die bonding processes and wire bonding processes, which may be continuously repeated with respect to each memory chip, tend to make the overall process complex.